1. Field of the Invention
The present invention relates to a circuit arrangement for time-division multiplex (TDM) telecommunications exchanges, in particular for pulse code modulation (PCM) telephone exchanges, wherein individual connections are, in each case, established via a pair of channels, the two individual channels of which serve to transmit communications relating to the connection in the one end and in the other direction of transmission, and with line trunk group (LTG) devices which are individually connected to the inputs of the multi-stage switching network and in which the two channels which are to be switched through across the switching network in accordance with the TDM principle and are each assigned to a connection exhibit synchronism in respect of time clock rate and pulse frame boundaries by virtue of the intermediate storage of the items of communication information to be transmitted in each of the two directions of transmission. The write-in processes and the read-out processes in the relevant full memories of these devices are brought into conformity with regard to the time sequence of the individual sub-items of information and with regard to the time position of the pulse frame boundaries of the pulse frames which serve to combine the sub-items of information scanning cycle-by-scanning cycle. Pairs of channels of this kind, which are switched-through on a TDM basis and which are each assigned to a connection are subject to delay influences in their course from one of the aforementioned devices across the switching network back to the same or to another of these devices which corresponds thereto and which operates in clock rate and pulse frame synchronism therewith. The delay influences relate to the time sequence of the individual sub-items of information and the time position of each of the pulse frame boundaries. Delay devices are provided by way of which the channels may be switched through on a TDM basis and which serve to implement an additional delay by which the sub-items of information which arrive via a channel of a pair of channels assigned to a connection from the switching network in the aforementioned device or the corresponding sub-items of information which are to be forwarded to the switching network via the other channel of the pair are brought into synchronism in respect of their time slots and the boundaries of their pulse frames, in order to assure the aforementioned synchronism.
2. Description of the Prior Art
Delay devices of the type mentioned above are known from the German Pat. No. 2,148,994. German Pat. No. 1,939,027, German Pat. No. 2,021,344 and German Pat. No. 2,109,038 are also concerned with the problem of so-called frame compensation which is discussed, for example, therein. Frame compensation is achieved with the aid of delay devices of the abovementioned type.
The delay devices comprise, for example, compensating memories, e.g. full memories into which sub-items of information arriving via the time channels of an incoming TDM line are written successfully in accordance with the correct time slot, and from which these sub-items of information are read in the sequence in which they were written following a storage time which corresponds to the desired delay, whereupon they are retransmitted by way of the outgoing TDM line connected to the compensating memory. Compensating memories of this kind can be designed so as to permit adjustment of their storage time. Consequently, their storage time may be adapted to existing requirements in respect of the prevailing operating situation. If, due to line influences or the like, sub-items of information arriving via a TDM line are affected by a delay of a specific delay time, the storage time and the compensating memory in question is designed to be such that the sum of delay time plus storage time is equal to the pulse frame duration--or a whole numbered multiple thereof--of the pulse frames in which the sub-items of information are transmitted via the TDM lines. In this manner, the boundaries of the pulse frames are shifted in time so that the boundaries of the pulse frames of the sub-items of information transmitted via various TDM lines coincide in time.
In switching networks of the type referred to above, and which are assumed to be known per se, switching network inputs are connected to so-called line trunk groups, which in the following will always be referred to with the abbreviation LTG (LTG being understood to be a terminal group for TDM connection lines or a terminal group for analog/digital and digital/analog converters and the like). The LTGs are likewise individually connected to switching network outputs. By way of the switching network inputs, the sub-items of information from the LTGs are transmitted in the direction of the switching network. By way of the switching network outputs, the sub-items of information transmitted via the switching network are forwarded in the direction of the LTGs. From the sub-items of information which are successively forwarded via the switching network outputs, in connection with pulse frames, and are received in the LTGs, the LTGs derive the operating clock rate which governs their internal switching functions, including the time slots of the pulse frame boundaries. On this basis, it is also possible to determine the time slots of the sub-items of information successively transmitted from the LTGs to the switching network internally within the pulse frames, including the time slots of the pulse frame boundaries of such pulse frames.
On the lines leading from the switching network to the LTGs, the sub-items of information transmitted across these lines are subject to line influences which result in a delay of the sub-items of information along the lines of the delay influences referred to above. In addition, the internal switching functions of the LTGs are affected by delay influences which result in a delay of the time slots of the sub-items of information transmitted from the LTGs to the switching network input in question in relation to the subitems of information transmitted from the switching network output to the LTG (operating clock rate derived from the switching network) including the time slots of the pulse frame boundaries. Finally, the sub-items of information transmitted from the LTGs to the switching network input in question are likewise subject to line influences, which again manifest as delays and can even result in a time shift of the appertaining pulse frame boundaries.
These delays which are thus produced at three stages can differ in magnitude depending upon the nature and the length of the lines concerned. Furthermore, the various LTGs can themselves exert different delay influences of the above-mentioned type. The delays caused by these factors and by the different line values remain constant while operation is in progress. Furthermore, however, in the LTGs, the device which serves to synchronize the LTG in question to the appertaining clock rate derived from the switching network (including time slots of the pulse frame boundaries) can be affected by a disturbance. Delays occurring in this manner within an LTG in respect of the sub-items of information transmitted from the LTG to the relevant switching network input in relation to the operating clock rate derived by the LTG from the sub-items of information transmitted from the relevant switching network output to the LTG, including the time slots of the pulse frame boundaries, therefore will not automatically remain constant while operation is in progress, but may not occur for a long period of time, or can occur at any time due to interference, and can also vary in magnitude during the course of operation.